There is a demand for faster, higher capacity, random access memory (RAM) devices. RAM devices, such as dynamic random access memory (DRAM) devices are typically used as the main memory in computer systems. Although the operating speed of the DRAM has improved over the years, the speed has not reached that of the processors used to access the DRAM.
Synchronous dynamic random access memory (SDRAM) has been developed to provide faster operation in a synchronous manner. SDRAMs are designed to operate synchronously with the system clock. That is, input and output data of the SDRAM are synchronized to an active edge of the system clock which is driving the processor accessing the SDRAM.
Double data rate (DDR) SDRAMs and second generation DDR SDRAMs, known as DDR II SDRAMs, are being developed to provide twice the operating speed of the conventional SDRAM. These devices allow data transfers on both the rising and falling edges of the system clock and thus, provide twice as much data as the conventional SDRAM.
Referring to FIG. 1, a portion of a DDR SDRAM integrated circuit 10 is shown. The SDRAM 10 includes a plurality of memory arrays 20a, 20b, 20c, 20d (collectively referred to herein as “arrays 20”) and peripheral circuitry 60 surrounding the arrays 20. Each array has a span (e.g., spans 22a, 22b) and includes, as shown in FIG. 2, multiple memory blocks 30 separated from each other in a first direction by a plurality of sense amplifiers 52, 54 (also referred to as sense amplifier stripes), and from each other in a second direction by a plurality of row drivers 42, 44. Accordingly each memory block 30 is bounded on two opposing sides by first and second sense amplifier stripes 52, 54 respectively. Further, each memory block 30 is bounded on two other opposing sides by first and second row driver stripes 42, 44 respectively. Gap cells 50 are located at the intersection of the row drivers 42, 44 and sense amplifier stripes 52, 54. The gap cells 50 may contain additional circuitry required by the arrays 20.
FIG. 3 illustrates a 128 megabit portion of the SDRAM circuit 10 consisting of a throat region 60 centrally located between two 64 megabit arrays 20a, 20b. The first array 20a contains at least one memory block 30a and sense amplifier circuit 52a. Digit lines 80a of the first array 20a are organized in a vertical direction while row lines 82a of the first array 20a are organized in a horizontal direction. The second array 20b contains at least one memory block 30b and sense amplifier circuit 52b. Digit lines 80b of the second array 20b are organized in a vertical direction while row lines 82b of the second array 20b are organized in a horizontal direction.
The throat 60 contains row logic 64 and a datapath 70. The row logic 64 contains LT drivers 62 and array drivers 66. The LT drivers 62 are global row decoders that drive LT lines 68 connected to the row drivers of both arrays 20a, 20b. As such, the LT drivers 62 are “bidirectional” (i.e., the LT driver 62 drive two different arrays 20a, 20b, the first array 20a being driven in a first direction and the second array 20b being driven in a second direction). The array drivers 66 include PH (phase), EQ (equilibration), ISO (isolation), NSA (n-sense amplifier control), PSA (p-sense amplifier control) drivers required to drive lines 67 connected to the sense amplifiers 52a, 52b. Thus, the row logic 64 of the throat 60 supports both arrays 20a, 20b in a bidirectional manner.
The illustrated datapath 70 contains IO circuits 72 having drivers for driving four IO pairs 74 connected to the first and second arrays 20a, 20b. As such, the datapath 70 and the IO circuits 72 are bidirectional. The illustrated SDRAM 10 uses four IO pairs 74 per block 30a, 30b to obtain a 2n pre-fetch. It is desirable to increase the number of IO pairs 74 and enhance the overall performance of the DDR SDRAM 10, while simplifying its architecture and the routing of the lines interconnecting the throat 60 and the arrays 20a, 20b. 
Moreover, although not shown in FIG. 3, the throat 60 and the arrays 20a, 20b share the same power bussing. With this configuration, power spikes and other sensitivities in the peripheral circuitry (e.g., throat 60) can adversely affect the array 20. Similarly, power spikes and other sensitivities in the arrays 20 can adversely affect the periphery, its IO circuitry and signal lines. Preventing noise from affecting the arrays 20 and the periphery will improve the performance of the SDRAM 10. Accordingly, there is a need and desire for a DDR SDRAM 10 with improved power bussing for the memory arrays 20 and peripheral circuitry (such as the throat 60).